A conventional CMOS image sensor has a floating diffusion layer and amplifier for each of pixels disposed in a matrix form. Column-parallel output types, where the output of the CMOS image sensor is obtained by selecting one row in the layout of pixels and reading these out in the column direction at the same time, are mainstream. Output read out in the column direction is converted into digital signals at an analog-to-digital converter at each column.
Various configurations have been conventionally proposed regarding analog-to-digital converters included in column-parallel output type CMOS image sensors. Of these, analog-to-digital converters that have a configuration where analog-to-digital conversion is performed on each of the two data pieces of initial state and after signal accumulation, and subtraction processing (digital CDS) of each of these is performed, thereby realizing low-noise characteristics, are mainstream. For example, PTL 1 discloses a technique where optimization of consumed current and circuit area are promoted by changing circuit configurations for high-order bits and low-order bits.
FIG. 15 is a block diagram illustrating a configuration example of a solid-state image sensor 101 in which conventional analog-to-digital converters disclosed in PTL 1 are included. The solid-state image sensor 101 includes a pixel portion 102, a row selecting circuit 103, a reference voltage generating unit 104, a counter generating unit 105, an analog-to-digital converter unit (ADC unit) 106, a column selecting circuit 107, and a signal processing unit 108, as illustrated in the drawing. The pixel portion 102 has multiple unit pixels 121. The ADC unit 106 has multiple analog-to-digital converters (ADCs) 161. Each ADC 161 has a comparator 162, a low-order bit latch unit 163, and a high-order bit counter unit 164.
The row selecting circuit 103 selects one row worth of unit pixels 121 out of the multiple rows within the pixel portion 2. The one row worth of unit pixels 121 that has been selected converts incident light into analog signals, and transfers the analog signals to the corresponding ADC unit 106 via corresponding vertical signal lines 122.
The reference voltage generating unit 104 generates reference voltage that varies based on a reference clock. The comparator 162 compares the input analog signal voltage with the reference voltage, and inverts the output signal at the point that the reference voltage exceeds the analog signal voltage. The counter generating unit 105 generates counter data 151. The low-order bit latch unit 163 latches the counter data 151, triggered at the point of the output signal of the comparator 162 being inverted. The low-order bit latch unit 163 generates a carry signal 165. The high-order bit counter unit 164 counts high-order bits in response to the carry signal 165.
Thus, the conventional solid-state image sensor 101 illustrated in FIG. 15 does not count low-order bits where there is a great amount of data transition, and latches counter data 151 generated by the count generating unit 105. This enables low-consumption current to be realized. Further, binary counting of high-order bits enables the circuit scale of the solid-state image sensor 101 to be reduced, since subtraction processing can be immediately performed.